1. Field of the Invention
The present invention relates to design tools used in development of application specific integrated circuit (ASIC) technology; and more particularly to techniques for performing timing analysis on circuit designs used in ASICs.
2. Description of the Related Art
Present electronic designing systems consist of software tools running on a digital computer that assist a designer in the creation and verification of complex electronic designs. Electronic computer-aided design (ECAD) systems are widely used in designing semiconductor integrated circuits. In particular, ECAD systems are used to generate data descriptive of the entire circuit layout as well as the layout of individual circuit cells. Since each cell often contains a large number of circuit elements and interconnections among the elements and their respective timing, ECAD systems have become an indispensable tool in the design of integrated circuits.
In the process of creating a large integrated circuit chip design, it is quite useful and customary to partition the logic into manageable pieces and to design hierarchically. This modularity maximizes reuse and simplifies the design. Some of the design pieces or blocks might be custom designed, while others could simply be synthesized ASIC blocks. If the design is to be processed by a timing analysis tool, such as a static timing analyzer, there must at least be timing information for each of the lowest level building blocks of the design. Timing information about these blocks is presented to the timing analysis tool in the form of timing rules.
There currently exist static timing analysis tools, which are commonly made available by vendors of ECAD stations and software, for timing analysis. Timing analysis is performed by software which analyzes the timing relationships between logic state changes within a circuit and determines if certain timing criteria such as minimum setup and hold times have been violated. A static timing analyzer does not attempt to model the circuit as it would operate but rather attempts to analyze a circuit""s temporal behavior.
ASIC level static timing analysis requires use of a xe2x80x9cnetlistxe2x80x9d describing the ASIC circuit to be timed, and timing rules. The netlist is a compilation of information descriptive of the primitives (i.e., circuit elements) of a logic circuit. Netlist can also be a cell description (a group of circuit elements) and their interconnection. The timing rules specify the timing for these circuits. Development and verification tools used in ASIC design usually implement a hardware description language. Static timing analysis use a number of industry standard formats for such netlists that include the Netlist Description Format (NDL), the Electronic Data Interchange Format (EDIF), etc. These netlist comprises a list of basic cells used in the design of the system, specifying interconnection among the cells. Connections between or among cells are known as nets. A circuit path through a system comprises a number of cells and the interconnecting nets for the circuit path. In most situations, this modeling provides adequate results, and the circuit can be timed reasonably well. However, a certain class of circuits having xe2x80x9copen channel inputsxe2x80x9d cannot be timed adequately using present forms of this analysis. Typically in complementary metal oxide semiconductor CMOS based logic circuits, the input pin(s) of a cell is connected to the GATE of a CMOS transistor. An xe2x80x9copen channel inputxe2x80x9d cell refers to a cell where the input pin(s) are connected to the source or drain of a CMOS transistor. In particular, using these conventional timing analytical frameworks for timing results, the load capacitance of each input pin on a particular circuit must be fixed. However, when a circuit has an open channel input, the load capacitance can have many different values. In some pathological situations, the load capacitance measured at the input to a circuit is not a function of that circuit. Instead, it is a function of that circuit and its electrical neighbors and interconnect connecting the circuit to its neighbors, commonly referred to as a static channel connected component (CCC).
To resolve such problems, a static-timing-analysis subsystem called transistor level timing (TLT) is used for timing such xe2x80x9copen channel inputxe2x80x9d circuits. Since TLT disregards gate boundaries, xe2x80x9copen channel inputxe2x80x9d problems do not exist. When TLT partitions a transistor circuit to analyze, this methodology divides the circuit so that no xe2x80x9copen channel inputsxe2x80x9d in the resulting partition exist.
FIG. 1 shows a conventional method of ASIC timing wherein a netlist is provided to a timer for generating a timing report from timing graphs using timing rules, capacitive parasitics and assertions. A NETLIST is an explicit list of cells and their interconnection. A TIMING RULE is a set of data and algorithms which specify the temporal behavior of a particular type of gate under different conditions, such as temperature, voltage, capacitive loading of signal outputs, and rate-of-change (slew) of signal input voltages. PARASITICS specify the electrical characteristics of the interconnections in the netlist, especially the resistance and capacitance. ASSERTIONS specify externally imposed timing constraints of the netlist. Conventional timing graphs for this method are shown in FIGS. 2a-2d as to how these timing graphs are constructed in association with an xe2x80x9copen channel inputxe2x80x9d problem.
Referring now to FIG. 1, the conventional timing processes is represented in a block diagram. Item 10 of the block diagram is the net list. An example of a net list is shown in FIG. 2a, discussed below. Item 208 illustrates timing rules that the net list 10 must comply with. Exemplary timing rules are shown in FIGS. 2c and 2d, discussed below. Additional variables such as parasitic capacitance 70 and assertions 60 are also shown in FIG. 1. Item 60 of this figure represent the external temporal requirements imposed on the netlist under analysis. These ASSERTIONS might include arrival times at the primary inputs to the netlist, and the arrival times required at the primary outputs of the netlist. In an item 100, these conventional systems build a timing graph with the information from the netlists 10 and the timing rules 208. An example of a timing graph is shown in FIG. 2b, discussed below. In item 90, the timing graph is annotated with the delays, arrival times and required arrival times using the information from the assertions 6, the parasitics 70, the timing graph and the timing rules 208.
In addition, the conventional process generates timing reports for the user using the timing graph and the netlist 10. A timing report is a text or graphical based summary of the temporal behavior of the netlist. This report may include the delay of the longest path through the netlist, an annotated list of the cells (and their individual delays) in the longest path, and the results of timing tests within the netlist and timing tests at the primary inputs and outputs of the netlist. The intent of the timing report is to concisely represent the critical timing(s) within the netlist, and alert the circuit designer to potential situations within the netlist that would prevent the proper operation of the netlist.
As mentioned above FIG. 2a illustrate a net list 200 that includes a first item 202 that is a box having a name A representing an inverter. Box 204 which has a name B and is a latch. The boxes are connected by a net 206 named C. The timing graph shown in FIG. 2b illustrates the input 210 to box A 202 and the output from box A 212. Once again the net 206 connecting the boxes 202, 204 is also shown in FIG. 2b. 
The data 214 and clock 216 inputs into box 204 and the output 218 from box 204 are also illustrated in FIG. 2b. 
FIG. 2c illustrates the timing rules for the inverter shown in box 202. Equation 2 in FIG. 2c represents a possible function for calculating the delay of the inverter. The data needed to calculate the delay is 210, and the results of the delay calculation are carried to the next box by 212. The delay of the inverter itself is 224.
Similarly, FIG. 2d illustrates the timing rules for the latch 204. Once again the data 214, clock 216 and output 218 are illustrated. As with FIG. 2c, the data and clock delays (226 and 228 respectively) are possibly calculated using equations 2, using the inputs 214 and 216. The details of these delay calculations are not germane to this invention, and hence are represented in prototypical fashion. However, present TLT methods are difficult to implement for an entire transistor design in view of its capacity constraints when compared to standard ASIC timing methods. Thus, this problem presents a need for less complex solutions in applying TLT to the entire ASIC design.
It is, therefore, an object of the present invention to provide an improved method for enhancing accuracy of static timing analysis of an application specific integrated circuit (ASIC).
Conventional systems performed circuit timing analysis using a standard net-based ASIC circuit timing analysis, which is a relatively quick analysis that calculates the circuit""s timing by using the timing rules of nets and the netlist, showing the connections between the nets. Also, a more intensive and slower TLT analysis is available. The TLT analysis looks at the actual design of the transistors themselves (and the actual wiring connections between the individual transistors) and uses this design to perform a timing analysis.
The TLT analysis is more complicated and slower than the net-based ASIC circuit timing analysis because the TLT makes individual calculations regarding the design of individual transistors. To the contrary, the net-based analysis begins with the known performance of a previously analyzed group of transistors that are grouped within a single hierarchical level, this group is termed a xe2x80x9cnetxe2x80x9d. Therefore, the net-based system uses a library of previous calculations for a group of wiring and devices as a starting point, while the TLT analysis makes such individual transistor/device calculations on its own.
In other words, the net-based analysis takes advantage of the hierarchical structure of libraries that contain know (previously calculated) individual net performance data, while the TLT analysis performs such calculations individually for each analysis. This makes the TLT analysis much slower than the net-based analysis and TLT analysis are not commonly used when net-based analysis are available. However, the present inventors have realized that for a specific group of circuits (xe2x80x9copen channel inputxe2x80x9d circuits) are not properly modeled by net-based analysis, principally because the load capacitance can have many different values in open channel input circuits. However, a TLT analysis will properly model such open channel input circuits. Therefore, to solve the above problem, the inventors have designed a system/method that checks circuits for open channel input circuits, and when such open channel input circuits are identified, the inventive system performs the slower, more intensive TLT analysis on the open channel input circuits.
Therefore, the invention takes advantage of the efficiencies associated with net-based ASIC timing analysis for most circuits. However, upon encountering an open channel input circuit, the invention switches modes and performs the more intensive TLT analysis to provide proper analysis for such circuits.
The invention provides a method and system for designing static timing analysis for application specific-type integrated circuits (ASIC). The method includes use of transistor level timing (TLT) methods that are used only when open channel circuit inputs are detected during the generation of the timing graph.
Thus, it is a further object to provide in an appropriately programmed computer, a static timing analysis method for generating a timing graph of an integrated circuit comprising inputting netlist, timing rules, open channel circuits, and transistor level design data into a timing analysis application; using said netlist to construct an initial timing graph for said integrated circuit; detecting at least one open channel circuit, while constructing said timing graph, and invoking transistor level timing (TLT) analysis for said open channel circuit(s) and static channel connected component (CCC); applying normal timing rules for circuits other than said open channel circuit(s) and said CCC, and using data from said TLT analysis and said normal timing rules to perform static timing analysis on said integrated circuit. The present invention also includes a computer implemented method implementing the method steps set forth above. The present invention also provides the advantage of a systematic generation of timing graphs used in designing an integrated circuit.